The present invention relates generally to address sequencers and more specifically to a Digital Signal Processing (DSP) address sequencer.
In Digital Signal Processing, there exist a need to generate an address to memories in various sequences. The sequences consist of: a) starting address, b) number of words in a block of addresses, c) number of blocks of addresses, d) increment between address blocks, and e) increments between addresses within a block. This assumes that all address blocks are uniform in length and uniformally distributed within a memory. This is generally the case. It is also desirable to set up a different sequence while the current sequence is being processed. Finally, it is desirable to make the structure capable of being tested without any additionally circuitry.
The prior art sequencers generally were microcoded sequencers or used various counters with fixed increment ratios or counts to determine when the next counter is to be incremented. An example is a maskable modulo counter PDSP1640 from Plessey Semiconductor.
Thus, it is object of the present invention to provide a more versatile address sequencer.
Another object of the present invention is to provide a sequencer which is not dependent upon fixed increments or counts.
Still a further object of the present invention is to provide an address sequencer which requires no additional circuitry for testing.
An even further object of the present invention is to provide a sequencer which is capable of setting up a different sequence while the current sequence is being processed.
These and other objects are obtained by providing an input structure for receiving and retaining sequential data which includes the sequence starting address, the number of blocks in the sequence, the number of words in a block, increment between blocks and increment between words, includes an adder connected between the input structure and an output device and includes a controller for selectively providing to the adder's inputs one or more of the sequence starting address, increment between words, increment between blocks and the output of the output device as a function of the number of blocks in the sequence and the number of words in a block. The controller begins a sequence by providing the sequence starting address to the adder. Subsequently the output of the output device and the increment between words in a block is provided to the adder for a plurality of cycles until the number of words within a block has been exceeded and then the increment between blocks and an address of the current block is provided to the adder. The previous two steps are repeated for plurality of cycles until the number of blocks of the sequence has been provided. An address of the current block to which the increment between blocks is to be added may be the last address of the block, which is available from the output device, or may be the starting address of the current block which is stored in a device at the beginning device of the cycle for the sequence for that block.
A first counter is provided for counting the number of cycles and a second counter for counting the number of blocks. The controller monitors the first counter to determine and reset it when the block size has been met and increments the second counter. Preferably the first and second counters are down counters and zero detectors are provided to produce the appropriate sequence and control. The sequence data is provided to input registers which are transferred to storage devices. This allows the information for more than one sequence to be stored and used. A pair of multiplexers are provided at the input of the adder such that the two inputs may be selectively produced. The output of the adder is connected directly to the output device, which is an output register, and may also be provided to a multiplexer which has a second input from the block size counter. This allows the output device to provide two independent addresses simultaneously for each cycle of operation.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.